Semiconductor memory devices, such as static random access memory (RAM) devices, commonly use burst mode operation to raise the efficiency of data access. During burst mode operation, internal addresses are sequentially generated upon receipt of an external address. During data reading or writing operations, rows of memory cells are then selected by the internal addresses. Thus, when selecting different rows of memory cells, a controller, such as a microprocessor, does not need to supply all the addresses in sequence. Instead, the controller may supply specific addresses for burst mode operation only once as the external addresses. To provide burst mode operation, a counter internal to the memory device sequentially generates a plurality of internal addresses based on a received external address. For example, static RAMs may receive 2 specific addresses and then generate 4 internal addresses using the counter.
Typically, the external addresses applied to a volatile semiconductor memory device having a typical redundancy scheme are provided to an address buffer and then to a normal decoder for normal operation and to a redundancy decoder for redundancy operation. The addresses generated by the address buffer are commonly controlled by an internal clock synchronized with an external clock.
FIG. 1 shows a conventional semiconductor memory device. If external addresses are applied to an address buffer 10, the external addresses may be separated into an address signal for normal operation and an address signal for redundancy operation by an address control clock which is the internal clock. The separated signals are respectively supplied to a normal decoder 14 and a redundancy decoder 12. The normal decoder 14 enables one selected word line among a plurality of normal word lines 16 within a memory cell array 18. The redundancy decoder 12 further receives a burst address and enables one selected word line among a plurality of redundancy word lines 20 within the memory cell array 18.
FIG. 2 is a detailed circuit diagram of the redundancy decoder 12 shown in FIG. 1. The redundancy decoder 12 includes master fuses MF, a plurality of internal fuses F, driving transistors N1-N3, N5, P1 and P2, decoding transistors N6 and N7, an output inverter INV and a decoding output NAND gate NAN1. To replace a normal word line connected to a defective cell with a redundancy word line, the redundancy decoder 12 receives external addresses A1-A5 and burst addresses C1 and C2 from a redundancy repair circuit therein (not shown). A redundancy word line enable signal RWL is generated at an output terminal of the NAND gate NAN1 (depending on whether the internal fuses F are cut to match the applied address {A1-A5, C1-C2}). This redundancy word line enable signal RWL enables a respective redundancy word line. Based on the decoding circuits of FIGS. 1-2, the address control clock K2 cannot be used in an internal circuit of the redundancy decoder 12, but is applied directly to the address buffer 10 situated at the front of the redundancy decoder 12. This is because there are two kinds of addresses applied to the redundancy decoder of FIG. 2. One address is the external address A1-A5 which is a normal address, and the other address is the burst address C1 and C2. However, when applying these separate addresses to the decoder 12 of FIG. 2, a normal address control clock may not be used together with a burst address control clock because the normal address control clock and the burst address control clock have opposite transitions. To address this limitation, the burst address control circuit of FIG. 3 is installed at the front of the redundancy decoder 12.
Referring to FIG. 3, there is shown a burst address control circuit for receiving address control clocks K1 and K2 and input burst signals RN1, RN2, RC1 and RC2 and generating a controlled burst address C1, C2. The burst address control circuit includes pass gates NA1-NA4 (containing inverters IN1-IN4) and inverters I10, I11, I20 and I21. If the semiconductor memory device is set in a normal mode of operation, an address controlled by the address control clock K2 is generated. Here, the least significant address bits C1 and C2 are set to RN1 and RN2 during the normal mode of operation. In a burst mode, a burst address controlled by the address control clock K1 is generated. Thus, during burst mode, C1 and C2 are set to RC1 and RC2. Here, the clocks K1 and K2 are active during alternating time intervals.
Therefore, in the conventional redundancy decoding scheme, the address control clock cannot be used in the interior of the redundancy decoder and so the burst address control circuit is additionally installed. Further, the burst address is generated by the burst address control circuit before being applied to the redundancy decoder. Therefore, the speed at which the redundancy word line can be enabled may be reduced.